Hardware Design

Architecture fundamentals such as processor type, memory structure, network-on-chip and resource availability must be thoroughly considered and specified, as they can have a dramatic impact on the overall system performance and cost. Careful partitioning of the system is crucial where hardware and software must be optimally tailored to a particular application.

Full Front-End design flow is executed from specification to logic synthesis passing through micro design modelled in a Hardware Description language.

Time to market (TTM) can be dramatically accelerated by intelligent IP Reuse coupled with a proven integration methodology. Pre-designed and verified hardware and software IPs such as embedded processors, network-on-chip, memory blocks, device drivers, kernels can be rapidly integrated in SoCs achieving large productivity gains and reduced TTM.

The rapid growth of the consumer market for battery-powered devices makes the incorporation of low-power design a necessity.  By outlining a SoC architecture at the highest level of abstraction and then further refining it through the many levels of abstraction, it is possible to continuously extract power savings towards the ultimate low power goal. Architecting for multiple power modes, various power domains, dynamic clock frequency can dramatically decrease the overall power of the system.

During development, architects and designers must remain fully aware of the power characteristics of their design. Dynamic power, static power and short circuit power should be continually analyzed and optimized to ensure that the final design will meet the lowest achievable power target.